Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

Author

Miro-Panades, Ivan ; Clermidy, Fabien ; Vivet, Pascal ; Greiner, Alain

Author_Institution

Univ. of Pierre et Marie Curie, Paris

fYear

2008

fDate

7-10 April 2008

Firstpage

139

Lastpage

148

Abstract

This paper presents a physical implementation of the DSPIN network-on-chip in the FAUST architecture. FAUST is a stream-oriented multi- application SoC platform for telecommunications addressing IEEE 802.11a and MC-CDMA standards. The original asynchronous network-on-chip (ANOC) of FAUST has been replaced by the multi-synchronous DSPIN network-on-chip. In this paper, we analyze how the DSPIN network-on-chip, originally designed to support shared memory and multi-processors architectures, can support stream-oriented architectures. The physical implementation of both ANOC and DSPIN are presented. Finally, a comparison between ANOC and DSPIN designs in a 130 nm technology is carried out in terms of area, throughput, packet latency, and power consumption.

Keywords

asynchronous circuits; memory architecture; network-on-chip; FAUST architecture; IEEE 802.11a standard; MC-CDMA standard; asynchronous network-on-chip; flexible architecture of unified systems for telecom; multiprocessors architecture; multisynchronous DSPIN network-on-chip; shared memory architecture; size 130 nm; stream-oriented multiapplication SoC; CMOS process; Clocks; Delay; Energy consumption; Frequency; Memory architecture; Multicarrier code division multiple access; Network-on-a-chip; Telecommunication standards; Throughput; ANOC; DSPIN; FAUST; NoC; bi-synchronous FIFO; network-on-chip; physical implementation;

fLanguage

English

Publisher

ieee

Conference_Titel

Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium on

Conference_Location

Newcastle upon Tyne

Print_ISBN

0-7695-3098-2

Type

conf

DOI

10.1109/NOCS.2008.4492733

Filename

4492733