DocumentCode
3292252
Title
A low-power 2.1 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic
Author
Yang, Ge ; Jung, Seong-Ook ; Kim, Soo Hwan ; Kang, Sung Mo
Author_Institution
California Univ., Santa Cruz, CA, USA
Volume
2
fYear
2002
fDate
4-7 Aug. 2002
Abstract
A high-speed, low-power 32-bit carry lookahead adder is presented. We have developed Dual Path All-N-Logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. This adder can operate at frequencies up to 2.1GHz for 0.35um 1P4M CMOS technology and is 31.3% and 27.3% faster than the adders using All-N-Transistor (ANT) and All-N-Logic (ANL), respectively. It also consumes 29.2% and 15.4% less power than the ANT adder and ANL adder, respectively.
Keywords
CMOS logic circuits; adders; high-speed integrated circuits; low-power electronics; 0.35 micron; 2.1 GHz; 32 bit; CMOS technology; Dual Path All-N-Logic; capacitance; dynamic circuit; high-speed low-power carry lookahead adder; Adders; CMOS logic circuits; CMOS technology; Capacitance; Clocks; Feedback; Frequency; MOS devices; MOSFETs; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1186857
Filename
1186857
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