Power and delay estimation for dynamic OR gates with header and footer transistor based on wavelet neural networks

A system for estimating the leakage power, the active power and the delay of the domino OR gates with the sleep transistor based on wavelet neural networks in 45 nm technology is proposed. By studying the impact of the power gating technique (PGT) on the power and delay characteristics, the proposed model could estimate the nonlinear changing of the active power, the leakage power and the delay of the different inputs dynamic OR gates with fast speed convergence and high precision. The trend of the estimating curve is discussed. At last, the comparison between the footer and the header sleep transistor technique is given.