Enabling Double Patterning at the 32nm Node

Most semiconductor manufacturers expect 193 nm immersion lithography to remain the dominant patterning technology through the 32 nm technology node. Conventional immersion lithography, however, is unlikely to take the industry to 32 nm half-pitch. Various double patterning techniques have been proposed to address this limitation. These solutions will combine design for manufacturability (DFM) and advanced process control (APC) strategies to achieve desired yield. Each strategy requires feeding forward design and process context and feeding back process metrics. In this work, we discuss interim solutions for control of double patterning lithography (DPL).