DocumentCode

3294087

Title

A Hierarchical Bridging Fault Extraction Approach For VLSI Circuit Layouts

Author

Chen, Tzuhao ; Hajj, Ibrahim N.

fYear

1997

fDate

3-5 June 1997

Firstpage

348

Lastpage

354

Keywords

Bridge circuits; Circuit faults; Circuit testing; Data mining; Logic circuits; Logic design; Logic gates; Logic testing; Routing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on

Conference_Location

Taipei, Taiwan

ISSN

1524-766X

Print_ISBN

0-7803-4131-7

Type

conf

DOI

10.1109/VTSA.1997.614932

Filename

614932