DocumentCode
3294257
Title
Manufacturing Challenges in Double Patterning Lithography
Author
Arnold, William ; Dusa, Mircea ; Finders, Jo
Author_Institution
ASML, Santa Clara
fYear
2006
fDate
25-27 Sept. 2006
Firstpage
283
Lastpage
286
Abstract
We present experimental and simulation results from investigating critical issues challenging Double Patterning lithography capability to meet manufacturing requirements for 45 nm 1/2 pitch on 0.93 NA lithography system. Simulations of lithography alternatives for positive and negative patterning processes based on focus-exposure metrics show that dual-line positive process has focus and exposure dose latitudes meeting manufacturing requirements. We introduced an innovative method to calculate double patterning CDU budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns. We achieved experimental double patterning minimum resolution of 40 /2 pitch on 0.93NA system, which equals 0.19kl. Predictive simulations indicate that double patterning overlay budget should be 70% or lower compared to single exposure application. Experimental overlay measurements on wafers exposed on state of the art 0.93NA system demonstrate current capability of ges 6 nm overlay with 53% probability to meet 4 nm overlay in single exposure applications and 30% probability to meet 4 nm overlay in a double patterning applications.
Keywords
manufacturing processes; nanolithography; nanopatterning; double patterning lithography; focus-exposure metrics; manufacturing challenges; negative patterning; state of the art system; wafers; Etching; Lithography; Manufacturing processes; Planarization; Predictive models; Protection; Resists; Rivers; Strips; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2006. ISSM 2006. IEEE International Symposium on
Conference_Location
Tokyo
ISSN
1523-553X
Print_ISBN
978-4-9904138-0-4
Type
conf
DOI
10.1109/ISSM.2006.4493084
Filename
4493084
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