DocumentCode
3294627
Title
Systematic deletion/insertion error correcting codes with random error correction capability
Author
Saowapa, Kiattichai ; Kaneko, Haruhiko ; Fujiwara, Eiji
Author_Institution
Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
fYear
1999
fDate
36465
Firstpage
284
Lastpage
292
Abstract
This paper presents a class of binary block codes capable of correcting single synchronization error and single reversal error with fewer check bits than the existing codes. This also shows a decoding circuit and analyzes its complexity
Keywords
binary codes; block codes; decoding; error correction codes; synchronisation; binary block codes; check bits; decoding circuit; existing codes; random error correction capability; single reversal error; single synchronization error; systematic deletion/insertion error correcting codes; Error correction codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on
Conference_Location
Albuquerque, NM
ISSN
1550-5774
Print_ISBN
0-7695-0325-x
Type
conf
DOI
10.1109/DFTVS.1999.802895
Filename
802895
Link To Document