Using nanoprobing and SEM doping contrast techniques for failure analysis of current leakage in CMOS HV technology

The method of substrate isolation in a typical CMOS HV technology with the addition of a deep nwell (DNW) is commonly applied in order to minimize the effect of disturbance in the substrate potential. The difficulties in identifying the true leakage path are, however, increasing as the noise current flows from this complex well structure with DNW employed in CMOS HV technology. This paper describes the use of nanoprobing and scanning electron microscope (SEM) doping contrast techniques to quickly and precisely pinpoint the leakage path.