General-purpose fast-switching PLL IC for frequency synthesis

This paper describes an integrated circuit implementation of the two-pulses speed-up method and proves by measurements, that the method can also be applied to fractional-N type synthesizers. The circuit (2.8×0.3 mm²) containing the speed-up circuitry, a PFD and a charge pump was fabricated in a 12 GHz doublepoly/double-metal BiCMOS process and uses 80 mA from a 5 V supply. The measured phase noise of an example integer-N synthesizer (f_out = 1.638 GHz and N = 126) is -102.3 dBc/Hz @ 10 kHz and the level of the 1st spurious at 13 MHz offset from the carrier is -67 dBc. Measurements of the speed-up circuitry show that the current pulse magnitude can be controlled by 7-bits, accuracy of which is mainly limited by switching transients and timing errors. The charge error between two similar current pulses is 0.27%, the result of which can be used to predict the exact settling behavior of the synthesizer.