A ROM based fractional-N frequency synthesizer for wireless communications

The wireless market has experienced an exponential growth over the past few years. To sustain this growth along with the increasing demands of new wireless standards the cost, battery lifetime, and performance of wireless devices must all be enhanced. With the advancement of radio frequency (RF) technology and requirement for more integration, new RF wireless architectures are needed. One of the most critical components in a wireless transceiver is the frequency synthesizer. It largely affects all three dimensions of a wireless transceiver design: cost, battery lifetime, and performance. The common approach to frequency synthesis design for wireless communication is to design an analog-compensated fractional-N phaselocked loop (PLL). However, this technique lacks of adequate fractional spurs suppression for third generation wireless standards. In this paper, a new ROM based sigma-delta PLL architecture is reported to enhance the above mentioned limitations. This architecture has all the benefits of the sigma-delta architecture in terms of fractional spurs reduction without its drawbacks like speed, power, cost, and stability. This aids in fully integrating a high-performance PLL frequency synthesizer, and hence reducing cost. The use of this architecture is examined to give a close match to the regular sigma-delta architecture in terms of noise shaping and measured spectrum at the VCO output.