Design and simulation of a 4 kV ESD protection circuit for a 0.8 mu m BiCMOS process

The authors present a novel ESD protection circuit that demonstrates 4 kV ESD protection in a BiCMOS process and show how to apply widely available simulation tools (TMA-PISCES and SPICE) to design this circuit. The protection circuit uses a novel triggering scheme by which an npn is able to protect the fully silicided, LDD (lightly doped drain) output nMOST. The npn is triggered by an nMOST injecting charge into the base. ESD stress data are obtained on control circuits to establish that the trigger transistor is indeed necessary. The authors also discuss other triggering schemes and general output protection strategies for advanced CMOS and BiCMOS circuits.<>