Modeling and design study of nanocrystal memory devices

Semiconductor memory for the future demand high density/low cost and low power consumption cell design. Compared with DRAM, flash memory with floating gate structure consume less power and they can also achieve much high array density. However, the tunnel oxide must be less than 25 Å in order to achieve 100 ns write/erase time for a reasonable programming voltage (<10 V). Unfortunately, the retention time of a floating-gate device with 20 Å tunnel oxide is less than 1 ms. To achieve a better retention/programming time ratio, a semiconductor memory with nanocrystal embedded in the gate dielectric was proposed. Although a nanocrystal memory device has been experimentally investigated, no theory is available to guide its design or to predict its performance limits, especially the nanocrystal size scaling limit. In this paper, the write/erase and retention time of semiconductor nanocrystal memory devices at room temperature are modeled using single-charge tunneling theory with quantum confinement and Coulomb blockade effects. The impact of nanocrystal size and tunnel-oxide thickness are studied, and the suitability of nanocrystal memory devices for nonvolatile memory and DRAM applications is discussed.