A 12-bit 1MS/s Non-calibrating SAR A/D Converter Based on 90nm CMOS Process

With a C-R combination based SAR (Successive Approximation Register) A/D conversion structure, a single-ended 12-bit 1MS/s non-calibrating SAR A/D converter is realized in UMC 90nm SP-RVT CMOS process. By using a two-segment resistor D/A architecture and careful layout routing approach, the capacitor’s matching requirement is alleviated. Instead of PIP and MIM capacitors, the metal finger capacitors are utilized to improve the technology compatibility. With a 3.3V analog supply and a 1.0V digital supply, the ENOB and DNL of this converter are measured to be 10.3 and 0.8LSB at the sampling rate of 1MS/s and the input frequency of 10 KHz. The power dissipation of this converter is measured to be less than 10mW and the active area is just about 0.31mm2.