Process-optimization for sub-30 ps BiCMOS technologies for mixed ECL/CMOS applications

Author

Klose, H. ; Kerber, M. ; Meister, T. ; Ohnemus, M. ; Kopl, R. ; Weger, P. ; Weng, J.

fYear

1991

fDate

8-11 Dec. 1991

Firstpage

89

Lastpage

92

Abstract

The authors present a 0.8 mu m BiCMOS technology for high-performance digital applications. The underlying optimization strategy to trade off both bipolar vs. CMOS speed and cutoff-frequency vs. collector-emitter breakdown voltage is described. Based on this approach 23.5 GHz cutoff frequency and 28 ps CML gate-delay times could be obtained for the bipolar device, making this technology perfectly suited for mixed CMOS/ECL (emitter-coupled logic) types of applications. This is additionally proved by high-speed benchmark circuits such as 2:1 frequency dividers operating up to 13.5 GHz.<>

Keywords

BiCMOS integrated circuits; digital integrated circuits; emitter-coupled logic; integrated circuit technology; integrated logic circuits; 0.8 micron; 23.5 GHz; 28 ps; 2:1 frequency dividers; BiCMOS technologies; CML gate-delay times; bipolar device; collector-emitter breakdown voltage; cutoff-frequency; emitter-coupled logic; high-performance digital applications; high-speed benchmark circuits; mixed ECL/CMOS applications; optimization strategy; Annealing; BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Degradation; Delay effects; Frequency conversion; Implants; Paper technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0243-5

Type

conf

DOI

10.1109/IEDM.1991.235417

Filename

235417