A room temperature CVD technology for interlayer in deep-submicron multilevel interconnection

Author

Homma, T. ; Murao, Y.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1991

fDate

8-11 Dec. 1991

Firstpage

289

Lastpage

292

Abstract

A novel interlayer dielectric film formation technology for multilevel interconnection by catalytic CVD (chemical vapor deposition) has been developed. This technique utilizes fluoro-triethoxy-silane (FSi(OC/sub 2/H/sub 5/)/sub 3/) and water vapor as source gases. It has been found that the film deposited at 25 degrees C has remarkably good properties, such as a small thermal stress increase, tightly bonded Si-O networks with no OH radicals, a small residual stress (50 MPa), a small dielectric constant

Keywords

CVD coatings; DRAM chips; VLSI; chemical vapour deposition; dielectric thin films; leakage currents; materials testing; metallisation; organic insulating materials; permittivity; polymer films; 0.5 micron; 1.0 micron; 16 Mbit; 25 C; DRAM; ULSI; catalytic CVD; chemical vapor deposition; crackfree film; dielectric constant; fluoro-triethoxy-silane; interlayer dielectric film formation; keyhole-free film; leakage current; multilevel interconnection; permittivity; planarization; properties; residual stress; room temperature CVD; source gases; step coverage; thermal stress; tightly bonded Si-O networks; water vapor; Bonding; Chemical technology; Chemical vapor deposition; Dielectric films; Gases; Residual stresses; Temperature; Thermal stresses; Water resources; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0243-5

Type

conf

DOI

10.1109/IEDM.1991.235446

Filename

235446