Top-Down Fabrication of Epitaxial SiGe/Si Multi-(Core/Shell) p-FET Nanowire Transistors

Author

Barraud, S. ; Hartmann, J.-M. ; Maffini-Alvaro, V. ; Tosti, L. ; Delaye, V. ; Lafond, D.

Author_Institution

LETI, Commissariat a l´Energie Atomique et aux Energies Alternatives, Grenoble, France

Volume

61

Issue

4

fYear

2014

fDate

Apr-14

Firstpage

953

Lastpage

956

Abstract

Short-gate length epitaxial Si_1-xGe_x/Si multi-(core/shell) p-type nanowire (NW) transistors with high-permittivity dielectric and metal gate were fabricated and their electrical properties examined. Silicon NWs were first of all patterned in ultrathin silicon-on-insulator wafers by lithography and etching. Selective epitaxial growth of Si_0.7Ge_0.3/Si or Si_0.7Ge_0.3/Si/Si_0.7Ge_0.3/Si shells was then performed around the Si NW core. Electrical transport measurements showed a hole mobility improvement up to 100% in Si_0.7Ge_0.3/Si/Si_0.7Ge_0.3/Si core/shell NWs (70% in wide planar devices) compared with p-type Si reference field effect transistors (FETs). Finally, a drive current enhancement of 60% compared with reference Si-channel devices was evidenced in multi-(core/shell) p-FET NWs scaled down to 15-nm gate length.

Keywords

Ge-Si alloys; MOSFET; epitaxial growth; etching; hole mobility; lithography; nanoelectronics; nanowires; permittivity; silicon; silicon-on-insulator; SiGe-Si-SiGe-Si; drive current enhancement; electrical transport measurements; epitaxial p-FET nanowire transistors; etching; high-permittivity dielectric; hole mobility improvement; lithography; metal gate; selective epitaxial growth; size 15 nm; top-down fabrication; ultrathin silicon-on-insulator wafers; Epitaxial growth; Logic gates; MOSFET; Silicon; Silicon germanium; Strain; Compressive strain; MOSFET; SiGe; core/shell; nanowire (NW); silicon-on-insulator (SoI);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2014.2306232

Filename

6747956