DocumentCode
3307248
Title
LogTM: log-based transactional memory
Author
Moore, Kevin E. ; Bobba, Jayaram ; Moravan, Michelle J. ; Hill, Mark D. ; Wood, David A.
Author_Institution
Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
fYear
2006
fDate
11-15 Feb. 2006
Firstpage
254
Lastpage
265
Abstract
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes providing data version management for the simultaneous storage of both new (visible if the transaction commits) and old (retained if the transaction aborts) values. Most (hardware) TM systems leave old values "in place" (the target memory address) and buffer new values elsewhere until commit. This makes aborts fast, but penalizes (the much more frequent) commits. In this paper, we present a new implementation of transactional memory, log-based transactional memory (LogTM), that makes commits fast by storing old values to a per-thread log in cacheable virtual memory and storing new values in place. LogTM makes two additional contributions. First, LogTM extends a MOESI directory protocol to enable both fast conflict detection on evicted blocks and fast commit (using lazy cleanup). Second, LogTM handles aborts in (library) software with little performance penalty. Evaluations running micro- and SPLASH-2 benchmarks on a 32-way multiprocessor support our decision to optimize for commit by showing that only 1-2% of transactions abort.
Keywords
cache storage; memory architecture; parallel architectures; parallel programming; transaction processing; virtual storage; MOESI directory protocol; SPLASH-2 benchmark; cacheable virtual memory; data version management; log-based transactional memory; parallel programming; software library; Concurrent computing; Hardware; Memory management; Parallel programming; Proposals; Protocols; Software libraries; Software performance; Software systems; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Computer Architecture, 2006. The Twelfth International Symposium on
ISSN
1530-0897
Print_ISBN
0-7803-9368-6
Type
conf
DOI
10.1109/HPCA.2006.1598134
Filename
1598134
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