Partial set for flip-flops based on state requirement for non-scan BIST scheme

This paper describes a methodology for improving sequential circuit´s testability in a pseudo-random testing environment. Our goal is to slightly modify the circuit under test with a DFT technique. For this, partial reset of circuit´s flip-flops is performed during application of the test sequence. Flip-flop candidates far reset and their reset period are chosen according to a methodology based on identification of required test states for hard-to-detect faults. By increasing the probability to reach these states, we improve the fault coverage.