A scalable coherent cache system with a dynamic pointing scheme

The author presents a scalable coherent cache scheme which is an interpolation between the full-vector scheme and the coarse-vector scheme. In contrast to the coarse vector, where each vector bit is used to represent a fixed number of processors, the new scheme uses a dynamic technique to enlarge and shift the bit vector so that the vector presents as few processors as possible with each vector bit. This technique allows the dynamic vector to be present only where it is used, which helps to reduce the amount of invalidation traffic. The author evaluates the new scheme using trace-driven simulation. The applications used for the evaluation represent a wide range of parallel algorithms written in different programming languages. The performance of the new scheme is presented in terms of execution time and invalidation traffic and is compared with the results for the full-vector, the coarse-vector, and the broadcast scheme. The new scheme performed in most of the cases as well as the full-vector scheme and in all cases better than all other limited-pointer schemes