• DocumentCode
    3312367
  • Title

    Record-low on-Resistance for 0.35 μm based integrated XtreMOSTM Transistors

  • Author

    Moens, P. ; Bauwens, F. ; Desoete, B. ; Baele, J. ; Vershinin, K. ; Ziad, H. ; Narayanan, E. M Shankara ; Tack, M.

  • Author_Institution
    AMI Semicond. Belgium, Oudenaarde
  • fYear
    2007
  • fDate
    27-31 May 2007
  • Firstpage
    57
  • Lastpage
    60
  • Abstract
    Experimental data are shown for integrated smart power transistors breaking the silicon limit at 100 V. The performance is close to the much lower super-junction limit for the given device pitch. The device uses standard trench technology, and is implemented in a 0.35 μm smart power process. Key steps to improve the device performance yielding a record performance of 30 mOhm*mm2 for a Vbd of 94 V, are highlighted in the paper.
  • Keywords
    power MOSFET; device pitch; integrated XtreMOS transistors; integrated smart power transistors; lower super-junction limit; record-low on-resistance; size 0.35 μm; voltage 100 V; voltage 94 V; Ambient intelligence; CMOS process; Implants; MOS capacitors; MOSFETs; Power semiconductor devices; Power transistors; Silicon; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on
  • Conference_Location
    Jeju Island
  • Print_ISBN
    1-4244-1095-9
  • Electronic_ISBN
    1-4244-1096-7
  • Type

    conf

  • DOI
    10.1109/ISPSD.2007.4294931
  • Filename
    4294931
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3312367