A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique

Author

Shuo-Hong Hung ; Wei-Hao Kao ; Kuan-I Wu ; Yi-Wei Huang ; Min-Han Hsieh ; Chen, Charlie Chung-Ping

Author_Institution

Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2015

fDate

24-27 May 2015

Firstpage

553

Lastpage

556

Abstract

An all-digital delay-locked loop (ADDLL) is proposed for wide range, fast lock, low jitter and high process-voltage-temperature (PVT) tolerance. The proposed phase tracking generator (PTG) produces two tracking rising and falling phases in only 2 cycles for fast lock and wide-range. The digital phase interpolator (DPI) and the control block are adopted to calibrate the phase offsets and random jitters while maintaining the closed-loop property that allow for tracking of PVT variations. The wide-range ADDLL operates from 160MHz to 2GHz. The measured peak-to-peak jitters are 6.89ps and 16.67ps at 2GHz and 160MHz. This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.205mm².

Keywords

delay lock loops; digital phase locked loops; jitter; all-digital delay-locked loop; control block; digital phase interpolator; frequency 160 MHz to 2 GHz; low jitter fast lock all-digital DLL; phase offsets; phase tracking generator; phase tracking technique; random jitters; size 90 nm; time 16.67 ps; time 6.89 ps; CMOS integrated circuits; Clocks; Delays; Detectors; Jitter; Logic gates; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7168693

Filename

7168693