Design and analysis of a low power consumption high speed frequency divider by 2/3

Author

Murtaza, Cristian ; Cojan, Radu Adrian

Author_Institution

Infineon Technol. Romania SCS, Bucharest, Romania

Volume

02

fYear

2010

fDate

11-13 Oct. 2010

Firstpage

449

Lastpage

452

Abstract

This paper presents the design and performances of two high speed high frequency dividers in a standard 60 nm RF technology. The dividers are part of a wireless receiver using a synthesizer with a reference frequency of 26 MHz and a voltage controlled oscillator with an output frequency of 6 GHz. The input operating frequency range of the dividers is 2-8 GHz. The minimum input voltage range is 250mV peak-to-peak and the power consumption of each divider is less than 0.4mW for a 1.3-V power supply.

Keywords

frequency dividers; frequency synthesizers; low-power electronics; microwave receivers; millimetre wave receivers; network synthesis; voltage-controlled oscillators; RF technology; frequency 2 GHz to 8 GHz; frequency 26 MHz; high-speed frequency divider; input operating frequency range; low-power consumption frequency divider; reference frequency; size 60 nm; voltage 1.3 V; voltage controlled oscillator; wireless receiver; Flip-flops; Frequency control; Frequency conversion; Frequency synthesizers; Phase locked loops; Phase noise; Power demand;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference (CAS), 2010 International

Conference_Location

Sinaia

ISSN

1545-827X

Print_ISBN

978-1-4244-5783-0

Type

conf

DOI

10.1109/SMICND.2010.5650526

Filename

5650526