Macromodel established by simulations for the analog regime of the avalanche gate-controlled diode

Author

Rusu, A. ; Ravariu, C. ; Rusu, Alex ; Dobrescu, D. ; Cozma, D.

Author_Institution

Fac. of Electron. Telecommun. & Inf. Technol., Politeh. Univ. of Bucharest, Bucharest, Romania

Volume

02

fYear

2010

fDate

11-13 Oct. 2010

Firstpage

419

Lastpage

422

Abstract

This paper presents the simulation results of the gate-controlled diode, working in the analog regime. The aim of the paper is to find the device macromodel that provides an optimum linearity of the junction voltage versus the gate voltage, at a given current. The lateral pn junction is simulated in the breakdown regime and the gate voltage biases the MOS capacitor in deep depletion. Finally, linearity under 1% was accomplished, being in agreement with the theory. An equivalent circuit was developed according to these simulations in order to be implemented in Spice like programs.

Keywords

MOS capacitors; avalanche diodes; equivalent circuits; p-n junctions; semiconductor device breakdown; semiconductor device models; MOS capacitor; SPICE like programs; analog regime; avalanche gate-controlled diode; breakdown regime; deep depletion; device macromodel; equivalent circuit; gate voltage; junction voltage; lateral pn junction; Breakdown voltage; Doping; Electric breakdown; Junctions; Logic gates; Semiconductor process modeling; Substrates; equivalent circuit; gated diode breakdown; simulations; unconventional MOS device;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference (CAS), 2010 International

Conference_Location

Sinaia

ISSN

1545-827X

Print_ISBN

978-1-4244-5783-0

Type

conf

DOI

10.1109/SMICND.2010.5650552

Filename

5650552