Design optimization for deep-submicron CMOS device at low temperature operation

Author

Kakumu, M. ; Peters, D. ; Liu, H.Y. ; Chiu, K.Y.

Author_Institution

Hewlett Packard Co., Palo Alto, CA, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

211

Lastpage

214

Abstract

Design optimization for 0.3 mu m channel CMOS technology at liquid-nitrogen temperature. (77 K) is described. The trade-off between circuit performance and reliability of deep submicrometer CMOS devices at low-temperature operation is theoretically and experimentally examined. A simulator has been developed which selects power-supply voltage and process/device parameters for low-temperature operation. Based on the simulated results, design optimization for low-temperature operation has been proposed to determine power-supply voltage and various process and device parameters. This scaling guideline has been applied to a 0.3 mu m CMOS device. Excellent device characteristics and a functional ring oscillator circuit have been obtained at 77 K.<>

Keywords

CMOS integrated circuits; cryogenics; digital simulation; integrated circuit technology; 03 micron; 77 K; circuit performance; deep-submicron CMOS device; design optimization; liquid-nitrogen temperature; low temperature operation; power-supply voltage; process/device parameters; reliability; scaling guideline; simulator; CMOS technology; Circuit optimization; Circuit simulation; Design optimization; Guidelines; Reliability theory; Ring oscillators; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237191

Filename

237191