DocumentCode
3318613
Title
A technology mapping algorithm for CPLD architectures
Author
Chen, Shih-Liang ; Hwang, TingTing ; Liu, C.L.
Author_Institution
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2002
fDate
16-18 Dec. 2002
Firstpage
204
Lastpage
210
Abstract
In this paper, we propose a technology mapping algorithm for CPLD architectures. Our algorithm proceeds in two phases: mapping for single-output PLAs and packing for multiple-output PLAs. In the mapping phase we propose a look-up-table (LUT) based mapping algorithm. We will take advantage of existing LUT mapping algorithms for area and depth minimization. Benchmark results show that our algorithm produce better results in terms of area and depth as compared to TEMPLA.
Keywords
logic CAD; minimisation of switching nets; programmable logic devices; table lookup; CPLD architectures; LUT; area minimization; depth minimization; look-up-table; multiple-output PLAs; single-output PLAs; technology mapping algorithm; Benchmark testing; Computer architecture; Delay; Field programmable gate arrays; Logic circuits; Logic devices; Minimization methods; Production; Programmable logic arrays; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on
Print_ISBN
0-7803-7574-2
Type
conf
DOI
10.1109/FPT.2002.1188683
Filename
1188683
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