A reliable bi-polarity write/erase technology in flash EEPROMs

Author

Aritome, S. ; Shirota, R. ; Kirisawa, R. ; Endoh, T. ; Nakayama, R. ; Sakui, K. ; Masuoka, F.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

111

Lastpage

114

Abstract

The authors describe a technology for scaling down the flash EEPROM cell, which has a conventional self-aligned double poly-Si stacked structure. It is clarified experimentally that a flash memory cell written and erased by Fowler-Nordheim (F-N) tunneling has ten times the retention time of the conventional cell, which is written by channel-hot-electron (CHE) injection and erased by F-N tunneling. This difference of data retentivity between these two write/erase (W/E) technologies is due to decreasing the thin gate oxide leakage current by bi-polarity F-N tunneling stress. This improvement in data retention becomes more pronounced as the gate oxide thickness decreases. Therefore, a bipolarity F-N tunneling WE technology, which enables a flash EEPROM cell to scale down its oxide thickness, shows promise as a key technology for realizing 16 Mb flash EEPROMs and beyond.<>

Keywords

EPROM; circuit reliability; hot carriers; integrated memory circuits; leakage currents; tunnelling; 16 Mbit; EEPROM cell; Fowler-Nordheim tunnelling; Si-SiO/sub 2/; bi-polarity write/erase technology; channel hot electron injection; data retentivity; double poly-Si stacked structure; flash memory cell; gate oxide thickness; leakage current; retention time; scaling down; self-aligned structure; Channel hot electron injection; EPROM; Flash memory cells; Leakage current; Stress; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237214

Filename

237214