A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods

Typical analytic placement methods seek to minimize total squared wirelength by solving a linear equation system. However, to avoid trivial solutions, certain blocks must be assigned locations on the Field Programmable Gate Array (FPGA) fabric prior to optimization. A simple way to achieve this is to assign blocks randomly. However, this does not always result in the best solution. In this paper, we present a novel algorithm, called ShrubPlace, for pre-assigning I/O blocks to I/O pads around the perimeter of the FPGA. To verify the efficacy of our pre-placement algorithm, we integrated the algorithm into the analytic placer. When tested with the 20 MCNC benchmarks, our results show a reduction in wirelength is possible, with very little additional execution time required to perform the pre-placement.