Channel Optimization for the Design of High Speed I/O links

Author

Mandrekar, Rohan ; Zhou, Yaping ; Chun, Sungjun ; Haridass, Anand ; Choi, Jinwoo ; Na, Nanju ; Dreps, Daniel ; Weekly, Roger ; Harvey, Paul

Author_Institution

IBM Corp., Austin, TX, USA

fYear

2010

fDate

3-7 Jan. 2010

Firstpage

87

Lastpage

92

Abstract

The continuous increase in microprocessor performance demands an equal order of increase in the bandwidth requirements on the memory and I/O interfaces. Providing the required bandwidth at an acceptable cost is a challenge to the system packaging engineer. This paper discusses how a passive channel can be optimized in a cost effective way to provide the maximum bandwidth. The paper focuses on the design methodology including modeling the channel, identifying the channel bottle-necks, optimizing around the bottle-necks and verifying the conclusions through simulation. Finally the simulation results are verified through hardware measurements.

Keywords

logic design; microprocessor chips; I/O interface; channel bottle-necks identification; channel optimization; high speed I/O links design; memory interface; microprocessor performance; Bandwidth; Costs; Design optimization; Frequency; Hardware; Microprocessors; Packaging; Signal processing; Systems engineering and theory; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2010. VLSID '10. 23rd International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

978-1-4244-5541-6

Type

conf

DOI

10.1109/VLSI.Design.2010.87

Filename

5401187