Speedup analysis in simulation-emulation co-operation

Author

Miremadi, Seyed Ghassem ; Sarmadi, Siavash Bayat ; Asadi, Ghazanfar

Author_Institution

Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran

fYear

2002

fDate

16-18 Dec. 2002

Firstpage

394

Lastpage

398

Abstract

This paper presents an analytical approach to estimate the speedup in a simulation-emulation cooperation environment. The speedup of this approach as compared with the speedup of a pure simulation is analyzed. Also, an analysis of the speedup is given when different types of application instructions are utilized. The analysis is based on using both Verilog and VHDL. The results show that when only the simulation part of the simulation-emulation co-operation is used, the speedup is higher, than when the pure simulation is used. The total speedup is also depended on the type of application instructions and the communication cycle time between the simulator and the emulator.

Keywords

formal verification; hardware description languages; logic simulation; VHDL; Verilog; application instructions; communication cycle time; simulation-emulation co-operation; speedup analysis; Analytical models; Circuit simulation; Computational modeling; Computer simulation; Controllability; Digital systems; Emulation; Hardware design languages; Logic; Observability;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on

Print_ISBN

0-7803-7574-2

Type

conf

DOI

10.1109/FPT.2002.1188719

Filename

1188719