A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO

We present the design flow for a P4VT (power-performance-process-parasitic-voltage-temperature) aware voltage controlled oscillator (VCO). Through simulations, we have shown that parasitics, process, voltage and temperature have a drastic effect on the performance (center frequency) of the VCO. A design optimization of the VCO, along with dual-threshold power minimization has been performed in the presence of worst-case variations. The end product of the proposed methodology is a P4VT-optimal dual-threshold 90 nm VCO layout. We have achieved 16.4% power (including leakage) minimization with 10% degradation in center frequency compared to the target frequency, in the presence of worst-case variations.