Accelerating Synchronous Sequential Circuits Using an Adaptive Clock

In this paper we propose a scheme for enhancing the timing performance of a pre-designed synchronous sequential circuit. In the proposed scheme, a circuit is driven by two clocks. One of them is the conventional clock while the other one, having a shorter period, is applied when the circuit stabilizes well before the critical delay. We use a symbolic algorithm to analyze the timing behavior of the synchronous sequential circuit and provide add-on circuitry to select the appropriate clock based on the current state of the circuit. We demonstrate an appreciable gain (67% in average) in timing performance on several benchmark circuits.