DocumentCode
3321509
Title
Effective wafer inspection strategy for memory manufacturing foundries with inspiring HARI results
Author
Lin, L. ; Chen, S. ; Man, T. ; Yang Hyong Ki
Author_Institution
Dept. of Yield Eng., Powerchip Semicond. Co., Hsin-Chu
fYear
2005
fDate
11-12 April 2005
Firstpage
38
Lastpage
42
Abstract
Yield monitoring has been and always will be one of the most important technologies in memory manufacturing foundries. The monitoring scheme is becoming drastically complicated. As the design rule surpasses the 90 nm regime, the types and sizes of defects are also getting extremely complex. New types of defects are discovered with emerging inspection technologies and a variety of defect inspection tools are available in the market today. However, the resolution cost for these tools are higher than the existing ones. To overcome the above problems, a new inspection scheme called combined inspection strategy is introduced. Defect review schemes were also studied to identify killer defect status more effectively. Potential benefits of the optimized monitoring strategy are detecting more excursions, obtaining meaningful information within a shorter period of time and reducing resolution costs
Keywords
cost reduction; foundries; inspection; integrated circuit yield; microprocessor chips; process monitoring; 300 mm; combined inspection strategy; defect inspection tools; defect review schemes; inspection technologies; memory manufacturing foundries; monitoring scheme; resolution costs reduction; wafer inspection strategy; yield monitoring; Costs; Foundries; Inspection; Manufacturing; Monitoring; Portfolios; Sampling methods; Semiconductor device manufacture; Semiconductor materials; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 2005 IEEE/SEMI
Conference_Location
Munich
Print_ISBN
0-7803-8997-2
Type
conf
DOI
10.1109/ASMC.2005.1438764
Filename
1438764
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