Delay performance of high-speed packet switches with low speedup

The speedup of a switch is the factor by which the switch, and hence the memory used in the switch, runs faster compared to the line rate. In high-speed switches, line rates are already touching the limits at which memory can operate. It is very important for a switch to run at as low a speedup as possible. For an input queued (IQ) switch at speedup 1, 100% throughput can be achieved for any admissible traffic (McKeown, N. et al., 1999; Dai, J. and Prabhakar, B., 2000). This gives finite average delays but does not guarantee control on packet delays. S.T. Chuang et al. (see IEEE J. Selected Areas of Commun., vol.17, no.6, p.1030-9, 1999) show that a combined input output queued (CIOQ) switch can emulate perfectly an output queued (OQ) switch at a speedup of 2 and, thus, control the packet delays. This motivates a study of the possibility of obtaining delay control at speedup less than 2. To guarantee optimal control of delays for a general class of traffic, as shown by Chuang et al., speedup 2 is necessary. Hence, to obtain control of delays at lower speedup, we need to restrict the class of arrival traffic. We study the speedup requirement for a class of admissible traffic, which we denote as (1, nF)-regulated traffic, with parameters n and F. We obtain the necessary speedup for this class of traffic. Further, we present a general class of algorithms working at the necessary speedups and thus providing bounded delays.