DocumentCode
3324483
Title
Winner-take-all neural network with digital frequency-locked loop
Author
Hikawa, Hiroomi
Author_Institution
Dept. of Electr. & Electron. Eng., Kansai Univ., Suita, Japan
fYear
2015
fDate
24-27 May 2015
Firstpage
2517
Lastpage
2520
Abstract
This paper proposes a new winner-take-all neural network (WTANN), in which input vector information is conveyed by frequency-modulated signals, and neuron computation is carried out by digital frequency-locked loops (DFLLs). The DFLL uses direct digital frequency synthesizer (DDS) as its local oscillator. Frequency resolution of signal generated by the DDS is decided by the size of internal register. Winner search operation is implemented by using frequency comparator circuit, and is distributed among all neurons. The proposed WTANN architecture was described in VHDL and its feasibility was verified by VHDL simulations. Preliminary simulation results show that the proposed SOM has good capability in classifying input vectors.
Keywords
comparators (circuits); direct digital synthesis; frequency locked loops; neural nets; digital frequency-locked loop; direct digital frequency synthesizer; frequency comparator circuit; frequency resolution; frequency-modulated signals; input vector information; internal register; neuron computation; winner search operation; winner-take-all neural network; Biological neural networks; Frequency control; Frequency locked loops; Neurons; Radiation detectors; Registers; Training; VHDL; frequency modulated signal; frequency-locked loop; winner takes all neural network;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location
Lisbon
Type
conf
DOI
10.1109/ISCAS.2015.7169197
Filename
7169197
Link To Document