Multi-channel implementation of G .729 A/B on FPGA

Traditionally, G.729 Annexure A and B and other speech codecs are implemented on programmable digital signal processors (DSPs). This paper presents the implementation of G.729 A/B on field programmable gate arrays (FPGAs). This implementation has improved performance in terms of computational delay and memory as compared to its implementation on DSPs. The advantage of reduction in the computational delay can allow additional channels in 10 ms time frame of G.729. The Architecture for G.729 A/B is highly optimized. It is used on Time-shared basis such that same hardware is used for encoding and decoding of speech signal frames. It is implemented on Xilinx´s Vertex-II Pro FPGA.