Delay testing with double observations [high-speed ICs]

Delay testing is important for high speed ICs. The main difficulty for delay testing comes from the huge number of paths and the large percentage of delay untestable paths. This paper presents an approach to delay testing with double observations, which provides a high path delay fault coverage by testing a small number of paths. But, for each test pair, it is necessary to sample the primary output twice, one before and another after the transition. The paper explains how to select the very limited number of paths, termed sample paths, and how to generate the test pair and the observation times for the sample paths. Furthermore, the number of sample paths is linear to the number of gates in the circuit under test, despite exponential growth in the number of single paths. Based on the analytical delay model, most of the paths are delay testable which makes the delay test generation easier than that based on single path sensitization