An efficient multi-operand addition structure

An efficient structure for multi-operand addition is proposed. This structure is based on adding n m-hit inputs in a manner that each stage generates carries given just to the next higher significant stage, i.e. the operation of each stage can be dependant only to one neighboring lower significant stage during the calculations. This structure results in an extreme reduction in hardware when the bit-width is much greater than the number of operands. The hardware size is reduced since it is not proportional to the bit-width of the inputs. Therefore, its area might become even smaller than a ripple carry word serial approach for large number of inputs. Finally, a parallel version of the proposed structure is introduced which produces the result in less delay (compared with the Kogge-Stone serial adder) at the cost of increasing the hardware area.