• DocumentCode
    332616
  • Title

    On speeding-up vector restoration based static compaction of test sequences for sequential circuits

  • Author

    Guo, Ruifeng ; Pomeranz, Irith ; Reddy, Sudhakar M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
  • fYear
    1998
  • fDate
    2-4 Dec 1998
  • Firstpage
    467
  • Lastpage
    471
  • Abstract
    We propose a technique to speed up restoration-based static test sequence compaction for synchronous sequential circuits. The proposed algorithm reverses the order of the test vectors during restoration. Specifically, every time a subsequence of T is restored to detect a subset of faults, the subsequence is placed at the end of the compacted sequence denoted by Tp. In this way, a fault detected by T p is guaranteed to remain detected by Tp at the end of the compaction process, and need not be resimulated as was the case with some of the earlier restoration based compaction methods. Experimental results presented in this paper demonstrate the effectiveness of the proposed procedure
  • Keywords
    automatic test pattern generation; binary sequences; fault simulation; logic testing; sequential circuits; vectors; compacted sequence; sequential circuits; speeding-up technique; static compaction; test sequences; vector restoration; Circuit faults; Circuit testing; Cities and towns; Compaction; Electrical fault detection; Fault detection; Heuristic algorithms; Sequential analysis; Sequential circuits; Synchronous generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
  • ISSN
    1081-7735
  • Print_ISBN
    0-8186-8277-9
  • Type

    conf

  • DOI
    10.1109/ATS.1998.741658
  • Filename
    741658