Power optimization of neural frontend interfaces

This paper presents a design methodology for power optimized neural frontend interfaces (NFIs). The minimum power is analytically derived based on the constituent building blocks of the NFI, namely low noise amplifier, programmable gain amplifier and analog-to-digital converter (ADC), all of which are bound by noise. In the optimization process two types of ADC are considered: the successive approximation register (SAR) and the comparator-based switched-capacitor (CBSC) cyclic converter. It is shown that for a resolution of 7 bits (optimum for spike sorting) the use of the CBSC cyclic ADC results in ~30% power reduction compared to the conventional SAR ADC. The derived minimum power limits take into account the accuracy requirements for spike sorting and are compared with a number of NFIs in the literature.