SDL to VHDL conversion rules: A case study

This paper´s aim is to contribute in the challenging task of defining and setting the basic rules that should be followed to transform a high abstraction level of a complicated system from one description scheme to another while keeping the system specification intact at correct. These rules, once defined, will be the basis upon which we build a tool that will be capable of transforming a certain system´s SDL presentation into a VHDL behavioral description, completely compliant with the original system specification and at the same time synthesizable which means that the huge gap existing between the outputs of nowadays tools for SDL to VHDL conversion will be narrowed, and the output (VHDL system presentation) will be flawless and available for industrial purposes and production. The differences between formal design languages, such as SDL, and implementation language, ex. VHDL, is pretty large, as usually SDl is concerned wit the algorithmic level, and the VHDL is synthesizable at the behavioral and structural levels.