Power aware channel width tapering of serially connected MOSFETs

In this paper a new transistor channel width tapering scheme called Hill tapering for FET chains is proposed with specific emphasis on power dissipation and layout area of the tapered chains. This tapering scheme results in the lowest power dissipation and physical area compared to any of the existing tapering schemes like linear, exponential or optimal tapering. It also offers high speed operation. The proposed scheme is general and can be used in all domino logic circuit designs. SPICE simulation results have shown that up to 81% power dissipation reduction could be achieved by using the proposed tapering scheme.