DORGA holographic memory architecture

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. However, in ORGAs, although a large virtual gate count can be realized by exploiting a large capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is still important to increase the instantaneous performance. In previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context occupied a large implementation area of the ORGA-VLSIs and thereby prevented the realization of large-gate-count ORGA-VLSIs. Therefore, to increase the gate density, a dynamic optically reconfigurable gate array (DORGA) architecture was proposed. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. This paper presents a perfect DORGA architecture including a holographic memory. The performance of the DORGA architecture, in particular the reconfiguration context retention time, was analyzed experimentally. The advantages of this architecture are discussed relative to the results of this study.