A graph-partitioning-based approach for multi-layer Constrained Via Minimization

We propose a novel layer assignment approach for the k-layer Constrained Via Minimization (CVM) problem. We transform the problem into a constrained k-way graph partitioning one. Practical issues such as pin-out constraint, over-the-cell constraint, and overlapping between wire segments of the same net, have all been taken into consideration. We propose a modified simulated annealing program for the problem. A set of large routing results generated by a commercial three-layer router has been used to test the effectiveness of the program. Up to 70% reduction of vias has been observed. Assuming an additional fourth layer is available, more reduction is achieved. This work is the first to demonstrate the feasibility of via minimization for practical sized multi layer layout. It is also applicable to future design with more layers.