Modeling and implementation of an N×N Clos-type interconnect network employing a `clashing´ control procedure

The authors present a model of an N×N (N=2ⁿ, an integer) Clos-type interconnect network using a `clashing´ control procedure. The control algorithm can be implemented in hardware and the time required to set up a permutation through the network is O(log₂N). Furthermore, the resulting network is nonblocking and rearrangeable; and an N×N network may be implemented on a (2N+5)- or (3N+5)-pin IC chip, depending on the exact implementation and control procedure