A limited-interconnect synthetic neural IC

A report is presented of the first design and simulation of a limited-interconnect, multilayered perceptron-like network. The network is isomorphic to fully connected layered architectures, but satisfies the interconnection length and density constraints imposed by VLSI technology. The authors show simulations that illustrate the ability of the architecture to generalize and tolerate faults. A very compact analog neural cell is described that can be fabricated on a production DRAM line. This chip architecture allows dynamic storage of weights, shunting inhibition, and pipelined behavior, and it readily scales to very large numbers of processing elements. A 512-element, feedforward neural chip is described.<>