DocumentCode
3330387
Title
Resistive bridge fault modeling, simulation and test generation
Author
Sar-Dessai, Vijay R. ; Walker, D.M.H.
Author_Institution
Intel Corp., Folsom, CA, USA
fYear
1999
fDate
1999
Firstpage
596
Lastpage
605
Abstract
In this work1 we develop models of resistive bridging faults and study the fault coverage on ISCAS85 circuits of different test sets using resistive and zero-ohm bridges at different supply voltages. These results explain several previously observed anomalous behaviors. In order to serve as a reference, we have developed the first resistive bridging fault ATPG, which attempts to detect the maximum possible bridging resistance at each fault site. We compare the results of the ATPG to the coverage obtained from other test sets, and coverage obtained by using the ATPG in a clean-up mode. Results on ISCAS85 circuits show that stuck-at test sets do quite well, but that the ATPG can still improve the coverage. We have also found that the loss of fault coverage is predominantly due to undetected faults, rather than faults in which only a small resistance is detected. This suggests that lower-cost fault models can be used to obtain high resistive bridge fault coverage
Keywords
automatic test pattern generation; fault simulation; integrated circuit testing; logic testing; table lookup; ATPG; ISCAS85 circuits; clean-up mode; cost; coverage; fault coverage; fault model; look-up table; maximum possible bridging resistance; resistive bridges; resistive bridging faults; simulation; stuck-at test sets; test generation; undetected faults; zero-ohm bridges; Automatic test pattern generation; Bridge circuits; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Logic testing; Predictive models; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1999. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-5753-1
Type
conf
DOI
10.1109/TEST.1999.805784
Filename
805784
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