Delay fault testing of IP-based designs via symbolic path modeling

Delay testing of designs that contain intellectual property (IF) cores is challenging. We propose a method that can test paths traversing both IP cores and user-defined blocks. It employs a highly efficient BDD-based path modeling method and an associated ATPG technique. Experimental results show that it robustly tests selected paths without using extra logic, and, at the same time, protects the intellectual property