DocumentCode
3331414
Title
Yield gain with memory BISR — a case study
Author
Karunaratne, Maddumage ; Oomann, Bejoy
Author_Institution
Univ. of Pittsburgh, Pittsburgh, PA, USA
fYear
2009
fDate
2-5 Aug. 2009
Firstpage
699
Lastpage
702
Abstract
We applied a BIST soft repair scheme to embedded memories using redundant data columns. We obtained yield and defect data from commercial silicon parts, and explored possible yield improvements with only a single bit repair. We implemented it on a chip with 90 memories and process margins were changed to obtain split lots to validate the repair scheme.
Keywords
built-in self test; embedded systems; logic testing; storage management chips; built-in self test; embedded memories; memory BIST; redundant data column; Built-in self-test; Circuit faults; Circuit testing; Costs; Fuses; Manufacturing; Process design; Random access memory; Redundancy; Silicon; BIST; Dynamic; Memory; Redundancy; Repair; Yield;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location
Cancun
ISSN
1548-3746
Print_ISBN
978-1-4244-4479-3
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2009.5235998
Filename
5235998
Link To Document