Cell-Aware Test

Author

Hapke, Friedrich ; Redemund, Wilfried ; Glowatz, A. ; Rajski, J. ; Reese, Michael ; Hustava, Marek ; Keim, Martin ; Schloeffel, Juergen ; Fast, Anja

Author_Institution

Mentor Graphics Dev. (Deutschland) GmbH, Hamburg, Germany

Volume

33

Issue

9

fYear

2014

fDate

Sept. 2014

Firstpage

1396

Lastpage

1409

Abstract

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.

Keywords

CMOS integrated circuits; MOSFET; automatic test pattern generation; failure analysis; integrated circuit testing; CMOS-based designs; FinFET technologies; automatic test pattern generation; cell-aware test; defect-oriented CAT fault model generation; failure analysis; transistor-level test; Automatic test pattern generation; Bridge circuits; Layout; Libraries; Logic gates; Resistors; Transistors; Automatic test pattern generation; FinFET test; cell-aware test; defect-based test; defective parts; design for testability; failure analysis; logic testing; test data compression; transistor-level test;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2014.2323216

Filename

6879635