Power aware combination of transposed-form and direct-form FIR polyphase decimators for Sigma-Delta ADCs

This paper introduces a novel selection criterion to choose between transposed and direct form filters for power efficient FIR polyphase decimators. Less than 5% tolerance between calculated power consumption using the proposed criterion and simulated results is observed. A combined architecture of transposed and direct form filters for power efficient FIR polyphase decimators is proposed. A decimator for a 3^rd order low-pass Sigma-Delta modulator with an oversampling ratio of 24 is used as a case study. Different topologies using both transposed and direct form structures have been implemented for power consumption investigation. The designs were synthesized in 0.13 mum CMOS technology.